Conventionally, there has been known a semiconductor nonvolatile memory in which complementary data are written to two memory cells, which has a blank check function.
For example, a semiconductor integrated circuit described in Japanese Patent Laying-Open No. 2009-272028 (PTD 1) is provided with a nonvolatile memory (DFL; 21) including a plurality of twin cells, a selector (SEL_BC), and a sense circuit (BC_SA). Complementary data are written to two nonvolatile memory cells (MC1, MC2) of each twin cell, to set the memory cells in a written state where one of the cells is set to low threshold voltage and the other cell is set to high threshold voltage. Non-complementary data are written (which is referred to as erasure) to the two nonvolatile memories (MC1, MC2), to set the memories in a blank state where both memories are set to low threshold voltage. The selector (SEL_BC) includes a plurality of switching elements. During a blank check operation, switching elements of the selector (SEL_BC) are controlled to be in an ON state, and a first total current of the twin cells commonly flowing to a first input terminal of the sense circuit is compared with a reference signal of a second input terminal, thereby detecting at high speed whether the plurality of twin cells are in the written state or in the blank state.